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1 ? 82c52 cmos serial cont roller interface the intersil 82c52 is a high performance programmable universal asynchronous receiver/transmitter (uart) and baud rate generator (brg) on a single chip. utilizing the intersil advanced scaled saji iv cmos process, the 82c52 will support data rates up to 1m baud asynchronously with a 16x clock (16mhz clock frequency). the on-chip baud rate generator can be programmed for any one of 72 different baud rates using a single industry standard crystal or external frequency source. a unique pre-scale divide circuit has been designed to provide standard rs-232-c baud rates when using any one of three industry standard crystals (1.8432mhz, 2.4576mhz, or 3.072mhz). a programmable buffered clock output (co) is available and can be programmed to provide eith er a buffered oscillator or 16x baud rate clock for gen eral purpose system usage. features ? single chip uart/brg ? dc to 16mhz (1m baud) operation ? crystal or external clock input ? on-chip baud rate generator - 72 selectable baud rates ? interrupt mode with mask capability ? microprocessor bus oriented interface ? 80c86 compatible ? single +5v power supply ? low power operation . . . . . . . . . . . . . . . . . . . . 1ma/mhz typ ? modem interface ? line break generation and detection ? operating temperature range: - c82c52 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0c to +70c - i82c52 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40c to +85c - m82c52. . . . . . . . . . . . . . . . . . . . . . . . . . . -55c to +125c ? pb-free plus anneal available (rohs compliant) ordering information 1m baud part marking temp range (c) package pkg. dwg. # cp82c52 cp82c52 0 to +70 pdip e28.6 cp82c52z (note) cp82c52z 0 to +70 pdip (pb-free)** e28.6 ip82c52 ip82c52 -40 to +85 pdip e28.6 cs82c5296 cs82c52 0 to +70 plcc (tape & reel) n28.45 cs82c52z* (note) cs82c52z 0to +70 plcc (pb-free) n28.45 is82c52 is82c52 -40 to +85 plcc n28.45 is82c52z* (note) is82c52z -40 to +85 plcc (pb-free) n28.45 id82c52 id82c52 -40 to +85 cerdip f28.6 md82c52/b md82c52/b -55 to +125 f28.6 8501501xa 8501501xa smd# f28.6 mr82c52/b -55 to +125 clcc j28.a 85015013a 85015013a smd# j28.a *add "96" suffix for tape and reel. **pb-free pdips can be used for through hole wave solder processing only. they are not intended for use in reflow solder processing applications. note: intersil pb-free plus anneal products employ special pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish , which are rohs compliant and compatible with both snpb and pb-free soldering operations. intersil pb-free products are msl classi fied at pb-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. data sheet fn2950.3 april 26, 2006 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 1997, 2002, 2006. all rights reserved all other trademarks mentioned are the property of their respective owners.
2 fn2950.3 april 26, 2006 pinouts block diagram 82c52 (pdip, cerdip) top view 82c52 (plcc, clcc) top view 28 27 26 25 24 23 22 21 20 19 18 17 16 15 rd wr d0 d1 d2 d3 d4 d5 d6 d7 a0 a1 ix ox 1 2 3 4 5 6 7 8 9 10 11 12 13 14 cso dr sdi intr rst co dtr dsr cts gnd sdo vcc tbre rts 23 24 25 22 21 20 19 11 3 2 1 4 14 15 16 17 18 12 13 28 27 26 10 5 6 7 8 9 d2 d3 d4 d5 d6 d7 a0 sdi intr rst tbre co rts dtr a1 ix ox sdo gnd dsr cts d1 d0 wr rd cso dr vcc read/write control logic data bus buffer program- mable boud rate control logic 3 - 10 1 2 11 12 rd wr a0 a1 28 cso 14 21 ox co 23 24 rst intr 13 ix generator internal data bus transmitter buffer register uart control and status receiver buffer register modem control and registers status registers 18 dsr 17 cts 19 dtr 20 rts transmitter register p receiver register p s 15 25 sdo sdi 22 26 tbre dr s d0-d7 82c52 82c52
3 fn2950.3 april 26, 2006 pin description symbol pin no. type active level description rd 1 i low read: the rd input causes the 82c52 to output data to the data bus (d0-d7). the data output depends upon the state of the address inputs (a0-a1). cs0 enables the rd input. wr 2 i low write: the wr input causes data from the data bus (d0- d7) to be input to the 82c52. addressing and chip select action is the same as for read operations. d0-d7 3-10 i/o high data bits 0-7: the data bus provides ei ght, three-state input/output lines for the transfer of data, control and status information between the 82c52 and the cpu. for character formats of less than 8 bits, the corresponding d7, d6 and d5 are consider ed ?don't cares? for data write operations and are 0 for data read operations. these lines are normally in a high impedance state except during read operations. d0 is the least significant bit (l sb) and is the first serial data bit to be received or transmitted. a0, a1 11, 12 i high address inputs: the address lines sele ct the various internal registers during cpu bus operations. ix, ox 13, 14 i/o crystal/clock: crystal connections for the internal baud rate generator. ix can also be used as an external clock input in which case ox should be left open. sdo 15 o high serial data output: serial data output from t he 82c52 transmitter circuitry. a mark (1) is a logic one (high) and space (0) is logic zero (low). sd0 is held in the mark condition when cts is false, when rst is true, when the transmitter register is empty, or when in the loop mode. gnd 16 low ground: power supply ground connection. cts 17 i low clear to send: the logical state of the cts line is reflected in the cts bit of the modem status register. any change of state in cts causes intr to be set true when inten and mien are true. a false level on cts will inhibit transmission of data on the sd0 output and will hold sd0 in the mark (high) state. if cts goes false during transmission, the curr ent character being transmitted will be completed. cts does not affect loop mode operation. dsr 18 i low data set ready: the logical state of the dsr line is reflected in the modem status register. any change of state of dsr will cause intr to be set if inten and mien are true. the state of this signal does not affect any other circuitry within the 82c52. dtr 19 o low data terminal ready: the dtr signal can be set (low) by writing a logic 1 to the appropriate bit in the modem control register (mcr). this signal is cleared (high) by writ ing a logic 0 in the dtr bit in the mcr or whenever a reset (rst = high) is applied to the 82c52. rts 20 o low request to send: the rts signal can be set (low) by writing a logic 1 to the appropriate bit in the mcr. this signal is cleared (high) by writing a logic 0 to the rts bit in the mcr or whenever a reset (rst = high) is applied to the 82c52. co 21 o clock out: this output is user programmable to provide either a buffered ix output or a buffered baud rate generator (16x) clock output. the buffered ix (crystal or external clock source) output is provided when the baud rate select register (brsr) bit 7 is set to a zero. writing a logic one to brsr bit 7 causes the co output to provide a bu ffered version of the internal baud rate generator clock which operates at sixteen times the programmed baud rate. on reset d7 (co select) is reset to 0. tbre 22 o high transmitter buffer register empty: the tbre output is set (high) whenever the transmitter buffer register (tbr) has transferred it s data to the transmit register. application of a reset (rst) to the 82c52 will also set the tbre output. tbre is cleared (low) whenever data is written to the tbr. rst 23 i high reset: the rst input forces the 82c52 into an ?idle? mode in which all serial data activities are suspended. the modem control register (mcr) along with its associated outputs are cleared. the uart status register (usr) is cleared except fo r the tbre and tc bits, which are set. the 82c52 remains in an ?idle? state until programmed to re sume serial data activities. the rst input is a schmitt triggered input. intr 24 o high interrupt request: the intr output is enabled by the inten bit in the modem control register (mcr). the mien bit selectively enables modem status changes to provide an input to the intr logic. figure 9 in design information shows th e overall relationship of these interrupt control signals. 82c52 82c52
4 fn2950.3 april 26, 2006 sdi 25 i high serial data input: serial data input to the 82c52 receiver circuits. a mark (1) is high, and a space (0) is low. data inputs on sdi are disabled when operating in the loop mode or when rst is true. dr 26 o high data ready: a true level indicates that a c haracter has been received, transferred to the rbr, and is ready for transfer to the cpu. dr is reset on a data read of the receiver buffer register (rbr) or when rst is true. v cc 27 high v cc : +5v positive power supply pin. a 0.1 f decoupling capacitor from v cc (pin 27) to gnd (pin 16) is recommended. cs0 28 i low chip select: the chip select input acts as an enable signal for the rd and wr input signals. pin description (continued) symbol pin no. type active level description 82c52 82c52
5 fn2950.3 april 26, 2006 reset during and after power-up, the 82c52 reset input (rst) must be held high for at least two ix clock cycles in order to initialize and drive the 82c52 circuits to an idle mode until proper programming can be done. a high on rst causes the following events to occur ? resets the internal baud rate generator (brg) circuit clock counters and bit counters. the baud rate select register (brsr) is not affected (except for bit 7 which is reset to 0). ? clears the uart status register (usr) except for transmission complete (tc) and transmit buffer register empty (tbre) which are set. the modem control register (mcr) is also cleared. all of the discrete lines, memory elements and miscellaneous logic associated with these register bits are also cleared or turned off. note that the uart control register (ucr) is not affected. following removal of the reset condition (rst = low), the 82c52 remains in the idle mode until programmed to its desired system configuration. programming the 82c52 the complete functional definition of the 82c52 is programmed by the systems soft ware. a set of control words (ucr, brsr and mcr) must be sent out by the cpu to initialize the 82c52 to support the desired communication format. these control words will program the character length, number of stop bits, even/odd/no parity, baud rate, etc. once programmed, the 82c52 is ready to perform its communication functions. the control registers can be written to in any order. however, the mcr should be written to last because it controls the interrupt enables, modem control outputs and the receiver enable bit. once the 82c52 is programmed and operational, these registers can be updated any time the 82c52 is not immediately transmitting or receiving data. table 1. shows the control signals required to access 82c52 internal registers. uart control register (ucr) the ucr is a write only register which configures the uart transmitter and receiver circuits. data bits d7 and d6 are not used but should always be set to a logic zero (0) in order to insure software compatibility with future product upgrades. during the echo mode, the transmitter always repeats the received word and parity, even when the ucr is programmed with different or no parity. see figure 1. baud rate select register (brsr) the 82c52 is designed to operate with a single crystal or external clock driving the ix input pin. the baud rate select register is used to select the divide ratio (one of 72) for the internal baud rate generator circuitry. the internal circuitry is separated into two separate counters, a prescaler and a divisor select. the prescaler can be set to any one of four division rates, 1, 3, 4, or 5. table 1. cs0 a1 a0 wr rd operation 00001data bus transmitter buffer register (tbr) 00010receiver buffer register (rbr) data bus 00101data bus uart control register (ucr) 00110uart status register (usr) data bus 01001data bus modem control register (mcr) 01010 mcr data bus 01101data bus bit rate select register (brsr) 01110modem status register (msr) data bus d7 d6 d5 d4 d3 d2 d1 d0 stop bit select 0 = 1 stop bits 1 = 1.5 stop bits (tx) and 1 stop bit (rx) if 5 data bits selected 1 = 2 stop bits for 6, 7 or 8 data bits selected parity control 000 = tx and rx even 001 = tx and rx odd 010 = tx even, rx odd 011 = tx odd, rx even 100 = tx even, rx check disabled 101 = tx odd, rx check disabled 11x = generation and check disabled word length select 00 = 5 bits 01 = 6 bits 10 = 7 bits 11 = 8 bits reserved set to 00 for future product upgrade compatibility figure 1. ucr 82c52 82c52
6 fn2950.3 april 26, 2006 the prescaler design has been optimized to provide standard baud rates using any one of three popular crystal frequencies. by using one of these common system clock frequencies, 1.8432mhz, 2.4576mhz or 3.072mhz and prescaler divide ratios of 3, 4, or 5 respectively, the prescaler output will provide a constant 614.4khz. when this frequency is further divided by the divisor select counter, any of the standard baud rates from 50 baud to 38.4kbaud can be selected (see table 2). non-standard baud rates up to 1mbaud can be selected by using different input frequencies (crystal or an external frequency input up to 16mhz) and/or different prescaler and divisor select ratios. regardless of the baud rate, the baud rate generator provides a clock which is 16 times the desired baud rate. for example, in order to operat e at a 1mbaud data rate, a 16mhz crystal, a prescale rate of 1, and a divisor select rate of ?external? would be used. this would provide a 16mhz clock as the output of the baud rate generator to the transmitter and receiver circuits. the co select bit in the brsr selects whether a buffered version of the external frequency input (ix input) or the baud rate generator output (16x baud rate clock) will be output on the co output (pin 21). the baud rate generator output will always be a 50% nominal duty cycle except when ?external? is selected and the prescaler is set to 3 or 5. note: these baud rates are based upon the following input frequency/ prescale divisor combinations. 1.8432mhz and prescale = 3 2.4576mhz and prescale = 4 3.072mhz and prescale = 5 ? all baud rates are exact except for: modem control register the mcr is a general purpose control register which can be written to and read from. the rts and dtr outputs are directly controlled by their associated bits in this register. note that a logic one asserts a true logic level (low) at these output pins. the interrupt enable (inten) bit is the overall control for the intr output pin. when inten is false, intr is held false (low). the operating mode bits conf igure the 82c52 into one of four possible modes. ?normal? configures the 82c52 for normal full or half duplex communications. ?transmit break?' enables the transmitter to only transmit break characters (start, data and stop bits all are logic zero). the echo mode causes any data that is received on the sdi input pin to be retransmitted on the sdo output pin. note that this output is d7 d6 d5 d4 d3 d2 d1 d0 prescaler select 00 = 1 01 = 3 10 = 4 11 = 5 divisor select 00000 = 2 00001 = 4 00010 = 16/3 00011 = 8 00100 = 32/3 00101 = 16 00110 = 58/3 00111 = 22 01000 = 32 01001 = 64 01010 = 128 01011 = 192 01100 = 256 01101 = 288 01110 = 352 01111 = 512 10000 = 768 11111 = external ( 1) co select 0 = ix output 1 = brg output (on reset, d7 (co select) is reset to 0) figure 2. brsr table 2. baud rate divisor 38.4k external 19.2k 2 9600 4 7200 16/3 4800 8 3600 32/3 2400 16 2000 ? 58/3 1800 ? 22 1200 32 600 64 300 128 200 192 150 256 134.5 ? 288 110 ? 352 75 512 50 768 baud rate actual percent error 1800 1745.45 3.03% 2000 1986.2 0.69% 134.5 133.33 0.87% 110 109.09 0.83% 82c52 82c52
7 fn2950.3 april 26, 2006 a buffered version of the data seen on the sdi input and is not a resynchronized output. al so note that normal uart transmission via the transmitter register is disabled when operating in the echo mode (see figure 4). the loop test mode internally routes transmitted data to the receiver circuitry for the purpose of self test. the transmit data is disabled from the sdo output pin. the receiver enable bit gates off the input to the receiver circuitry when in the false state. modem interrupt enable will permit any change in modem status line inputs (cts , dsr ) to cause an interrupt when this bit is enabled. bit d7 must always be written to with a logic zero to insure corre ct 82c52 operation. uart status register (usr) the usr provides a single re gister that the controlling sys tem can examine to determine if errors have occurred or if other status changes in the 82c5 2 require attention. for this reason, the usr is usually the fi rst register read by the cpu to determine the cause of an interrupt or to poll the status of the 82c52. three error flags oe, fe and pe report the status of any error conditions detected in the receiver circuitry. these error flags are updated with every character received during reception of the stop bits. the overrun error (oe) indicates that a character in the receiver register has been received and cannot be transferred to the receiver buffer register (rbr) because the rbr was not read by the cpu. framing error (fe) indicates that the last character received in the rbr contained improper stop bits. this could be caused by the absence of the required stop bi t(s) or by a stop bit(s) that was too short to be properly detected. parity error (pe) indicates that the last character received in the rbr contained a parity error based on the programmed parity of the receiver and the calculated parity of the received character data and parity bits. the received break (rbrk) status bit indicates that the last character received was a break character. a break character would be considered to be an invalid data character in that the entire character including parity and stop bits are a logic zero. the modem status bit is set whenever a transition is detected on any of the modem input lines (cts or dsr ). a subsequent read of the modem status register will show the state of these two signals. assertion of this bit will cause an interrupt (intr) to be generated if the mien and inten bits in the mcr register are enabled. the transmission complete (tc) bit indicates that both the tbr and transmitter registers are empty and the 82c52 has completed transmission of the last character it was commanded to transmit. the assertion of this bit will cause an interrupt (intr) if the inten bit in the mcr register is true. the transmitter buffer register empty (tbre) bit indicates that the tbr register is empt y and ready to receive another character. the data ready (dr) bit indicates that the rbr has been loaded with a received character (including break) and that the cpu may access this data. assertion of the tbre or dr bits do not affect the intr logic and associated intr output pin since the 82c52 has been designed to provide separate requests via the dr and tbre output pins. if a single interrupt for any status change in the 82c52 is desired this can be accomplished by using an 82c59a interrupt controller with dr, tbre, and intr as inputs. (see figure 11). d7 d6 d5 d4 d3 d2 d1 d0 request to send (rts) 0 = rts output high ? 1 = rts output low data terminal ready (dtr) 0 = dtr output high 1 = dtr output low interrupt enable (inten) 1 = interrupts enabled 0 = interrupts disabled mode select 00 = normal 01 = transmit break 10 = echo mode 11 = loop test mode receiver enable (ren) 0 = not enabled 1 = enabled modem interrupt enable (mien) 0 = not enabled 1 = enabled must be set to a logic 0 for normal 82c52 operation ? see modem status register desc ription for a description of register flag images with respect to output pins. figure 3. mcr figure 4. loop and e cho mode functionality serial data from transmitter register echo mode serial data to receiver register sdo pin 15 sdi pin 25 loop mode 82c52 82c52
8 fn2950.3 april 26, 2006 modem status register (msr) the msr allows the cpu to read the modem signal inputs by accessing the data bus interf ace of the 82c52. like all of the register images of external pins in the 82c52, true logic levels are represented by a high (1) signal level. by following this consistent definition, th e system software need not be concerned with whether external signals are high or low true. in particular, the modem signal inputs are low true, thus a 0 (true assertion) at a modem in put pin is represented by a 1 (true) in the msr. any change of state in any modem input signals will set the modem status (ms) bit in the usr register. when this happens, an interrupt (intr) wil l be generated if the mien and inten bits of the mcr are enabled. the data set ready (dsr) input is a status indicator from the modem to the 82c52 which indicates that the modem is ready to provide received data to the 82c52 receiver circuitry. clear to send (cts) is both a status and control signal from the modem that tells the 82c52 that the modem is ready to receive transmit data from the 82c52 transmitter output (sdo). a high (false) level on this input will inhibit the 82c52 from beginning transmission and if asserted in the middle of a transmission will only permit the 82c52 to finish transmission of the current character. receiver buffer register (rbr) the receiver circuitry in the 82c52 is programmable for 5, 6, 7 or 8 data bits per character. for words of less than 8 bits, the data is right justified to the least significant bit (lsb = d0). bit d0 of a data word is always the first data bit received. the unused bits in a less than 8-bit word, at the parallel interface, are set to a logic zero (0) by the 82c52. received data at the sdi input pin is shifted into the receiver register by an internal 1x clock which has been synchronized to the incoming data based on the position of the start bit. when a complete character has been shifted into the receiver register, the assembled data bits are parallel loaded into the receiver buffer register. both the dr output pin and dr flag in the usr register are set. this double buffering of the received data permits continuous reception of data without losing any of the received data. while the receiver register is shifting a new character into the 82c52, the receiver buff er register is holding a previously received characte r for the system cpu to read. failure to read the data in the rbr before complete reception of the next character can result in the loss of the data in the receiver register. the oe flag in the usr register indicates the overrun condition. transmitter buffer register (tbr) the transmitter buffer register (tbr) accepts parallel data from the data bus (d0-d7) and holds it until the transmitter register is empty and ready to accept a new character for d7 d6 d5 d4 d3 d2 d1 d0 parity error (pe) 0 = no error 1 = error framing error (fe) 0 = no error 1 = error overrun error (oe) 0 = no error 1 = error received break (rbrk) 0 = no break 1 = break modem status (ms) 0 = no status change 1 = status change transmission complete (tc) 0 = not complete 1 = complete transmitter buffer register empty (tbre) 0 = not empty 1 = empty data ready (dr) 0 = not ready 1 = ready figure 5. usr d7 d6 d5 d4 d3 d2 d1 d0 clear to send (cts) 0 = false 1 = truer data set ready (dsr) 0 = false 1 = true 0 0 undefined figure 6. msr d7 d6 d5 d4 d3 d2 d1 d0 bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 figure 7. rbr 5-bit word 6-bit word 7-bit word 8-bit word 82c52 82c52
9 fn2950.3 april 26, 2006 transmission. the transmitter always has the same word length and number of stop bits as the receiver. for words of less than 8 bits the unused bits at the microprocessor data bus are ignored by the transmitter. bit 0, which corresponds to d0 at the data bus, is always the first serial data bit transmitted. provision is made for the transmitter parity to be the same or different from the receiver. the tbre output pin and flag (usr register) reflect the status of the tbr. the tc flag (usr register) indicates when both tbr and tr are empty. 82c52 interrupt structure the 82c52 has provisions for software masking of interrupts generated for the intr output pi n. two control bits in the mcr register, mien and inten, control modem status interrupts and overall 82c52 interrupts respectively. figure 9 illustrates the logical control function provided by these signals. the modem status inputs (dsr and cts ) will trigger the edge detection circuitry with any change of status. reading the msr register will clear the detect circuit but has no effect on the status bits themselves. these status bits always reflect the state of the input pins regardless of the mask control signals. note that the st ate (high or low) of the status bits are inverted versions of the actual input pins. the edge detection circuits for the usr register signals will trigger only for a positive edge (true assertion) of these status bits. reading the usr register not only clears the edge detect circuit but also clears (sets to 0) all of the status bits. the output pins associated with these status bits are not affected by reading the usr register. a hardware reset of the 82c52 sets the tc status bit in the usr. when interrupts are subsequently enabled an interrupt can occur due to the fact that the positive edge detection circuitry in the interrupt logic has detected the setting of the tc bit. if this interrupt is not desired the usr should be read prior to enabling interrupts. this action resets the positive edge detection circuitry in the inte rrupt control logic (figure 9). note: for usr and msr, the setting of status bits is inhibited during status register read oper ations. if a status condition is generated during a read operation, the status bit is not set until the trailing edge of the rd pulse. if the bit was already set at the time of the read operation, and the same status condition occurs, that status bit will be cleared at the trailing edge of the rd pulse instead of being set again. software reset a software reset of the 82c52 is a useful method for returning to a completely known state without exercising a complete system reset. such a reset would consist of writing to the ucr, brsr and mcr registers. the usr and rbr registers should be read prior to enabling interrupts in order to clear out any residual data or status bits which may be invalid for subsequent operation. crystal operation the 82c52 crystal oscillator circuitry is designed to operate with a fundamental mode, parallel resonant crystal. this circuit is the same one used in the intersil 82c84a clock generator/driver. to summarize, table 3 and figure 10 show the required crystal parameters and crystal circuit configuration respectively. when using an external clock so urce, the ix input is driven and the ox output is left open. power consumption when using an external clock is typically 50% of that required when using a crystal. this is due to the sinusoidal nature of the drive circuitry when using a crystal. d7 d6 d5 d4 d3 d2 d1 d0 bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 figure 8. tbr 5-bit word 6-bit word 7-bit word 8-bit word table 3. parameter typical crystal specification frequency 1.0 to 16mhz type of operation parallel resonant, fundamental mode load capacitance (cl) 20 or 32pf (typ) r series (max) 100 ? (f = 16mhz, cl = 32pf) 200 ? (f = 16mhz, cl = 20pf) figure 9. 82c52 interrupt structure rd (msr) rbrk, tc oe, fe, pe (usr) rd (usr) dsr , cts (msr) intr pin 24 inten (mcr) mien (mcr) pos. edge detect pos. or neg. edge detect 82c52 82c52
10 fn2950.3 april 26, 2006 82c52 - 80c86 interfacing the following example (figure 11) shows the interface for an 82c52 in an 80c86 system. use of the intersil cmos interr upt controller (82c59a) is optional and necessary only if an interrupt driven system is desired. by using the intersil cmos 82c84a clock generator, the system can be built with a singl e crystal providing both the processor clock and the clock for the 82c52. the 82c52 has special divider circuitry which is designed to supply industry standard baud rates with a 2.4576mhz input frequency. using a 15mhz crystal as shown, results in less than a 2% frequency error which is adequate for many applications. for more precise baud rate requirements, a 14.7456mhz crystal will drive the 80c86 at 4.9mhz and provide the 82c52 with the standard baud rate input frequency of 2.4576mhz. if baud rates above 156kbaud ar e desired, the osc output can be used instead of the pclk ( 6) output for asynchronous baud rates up to 1mbaud. note: c1 = c2 = 20pf for cl = 20pf c1 = c2 = 47pf for cl = 32pf figure 10. c1 (note) gnd c2 (note) ix ox 82c52 figure 11. 80c86/82c52 interface 15mhz x1 x2 clk pclk osc 82c84a or 82c85 int inta clk 80c86 or 80c88 5mhz int irx 82c59a sdo sdi ix 82c52 cso inta ad0, ad7 2.5mhz 15mhz 82c88 (max mode) iord iowr address bus 2 chip select 3 serial data d0-d7 a0, a1 rd wr intr, dr, tbre 82c52 82c52
11 fn2950.3 april 26, 2006 absolute maximum rati ngs thermal information supply voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +8.0v input, output or i/o voltage . . . . . . . . . . . . gnd-0.5v to v cc +0.5v esd classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . class 1 operating conditions operating voltage range . . . . . . . . . . . . . . . . . . . . . +4.5v to +5.5v operating temperature range c82c52 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0c to +70c i82c52 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40c to +85c m82c52 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-55c to +125c thermal resistance (typical, note 1) ja (c/w) jc (c/w) cerdip package . . . . . . . . . . . . . . . . 45 8.4 clcc package . . . . . . . . . . . . . . . . . . 60 14 pdip package . . . . . . . . . . . . . . . . . . . 55 n/a plcc package . . . . . . . . . . . . . . . . . . 46 n/a maximum junction temperature ceramic package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175c plastic package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150c maximum storage temperature range . . . . . . . . . -65c to +150c maximum lead temperature (soldering 10s) . . . . . . . . . . . . +300c (lead tips only for surface mount packages) die characteristics gate count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1500 gates caution: stresses above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. note: 1. ja is measured with the component mount ed on an evaluation pc board in free air. dc electrical specifications v cc = 5.0v 10%, t a = 0 c to +70 c (c82c52), t a = -40 c to +85 c (l82c52) t a = -55 c to +125 c (m82c52) symbol parameter min max units test conditions v ih logical one input voltage 2.0 - v i82c52, c82c52 2.2 - v m82c52 v il logical zero input voltage - 0.8 v vth schmitt trigger logic one input voltage v cc -0.5 - v reset input vtl schmitt trigger logic zero input voltage - gnd +0.5 v reset input vih (clk) logical one clock input voltage v cc -0.5 - v external clock vll (clk) logical zero clock input voltage - gnd +0.5 v external clock voh output high voltage 3.0 - v i oh = -2.5ma, except ox v cc -0.4 - v i oh = -100 a, for ox - i oh = -1.0ma vol output low voltage - 0.4 v l ol = +2.5ma ii input leakage current -1.0 +1.0 av in = gnd or v cc , dip pins 1, 2, 11, 12, 17, 18, 23, 25, 28 io input/output leakage current -10.0 +10.0 av o = gnd or v cc , dip pins 3-10 iccop operating power supply current (note 1) - 4 ma external clock f = 2.4576mhz, v cc = 5.5v, v in = v cc or gnd, outputs open iccsb standby supply current - 100 av cc = 5.5v, v in = v cc or gnd, outputs open note: 1. guaranteed and sampled, but not 100% tested. iccop is typically 1.5ma/mhz. capacitance t a = 25 c symbol parameter typical units test conditions cin input capacitance 12 pf freq = 1mhz, all measurements are referenced to device gnd cout output capacitance 15 pf ci/o i/o capacitance 15 pf 82c52 82c52
12 fn2950.3 april 26, 2006 ac electrical specifications v cc = 5.0v 10%, t a = 0 c to +70 c (c82c52), t a = -40 c to +85 c (l82c52) t a = -55 c to +125 c (m82c52) timing requirements and responses symbol parameter min max units test conditions (1) tsvctl select setup to control leading edge 30 - ns (2) tcthsx select hold from control trailing edge 50 - ns (3) tctlcth control pulse width 150 - ns control consists of rd or wr (4) tcthctl control disable to control enable 190 - ns (5) trldv read low to data valid - 120 ns 1, see ac test circuit (6) trhdz read disable 0 60 ns 2, see ac test circuit (7) tdvwh data setup time 50 - ns (8) twhdx data hold time 20 - ns (9) fc clock frequency 0 16 mhz tchcl + tclch must be 62.5ns (10) tchcl clock high time 25 - ns (11) tclch clock low time 25 - ns (12) tr/tf ix input rise/fall time (external clock) - tx ns whichever is smaller (13) tfco clock output fall time - 15 ns cl = 50pf (14) trco clock output rise time - 15 ns cl = 50pf tx 1 6fc ----------- - or 50ns ac testing input, output waveforms figure 12. propagation delay fig ure 13. enable/disable delay ac testing: all input signals (except ix and rst) must switch between v il -0.4v and v ih +0.4v. input rise and fall times are driven at 1ns/v. input v ih + 0.4v v il - 0.4v 1.5v 1.5v v oh v ol output 90% 10% output 82c52 82c52
13 fn2950.3 april 26, 2006 timing waveform ac test circuit figure 14. bus operation cs0 , a0, a1 select valid next bus cycle wr rd d0-d7 d0-d7 (5) trldv (6) trhdz (1) tsvctl (3) tctlcth (4) tcthctl (1) tsvctl (3) tctlcth (2) tcthsx (8) twhdx (7) tdvwh valid write operation read operation test point r1 v1 cl output from device under test r2 test condition v1 r1 r2 cl 1 propagation delay 1.7v 520 100pf 2 disable delay v cc 5k 5k 50pf 82c52 82c52
14 fn2950.3 april 26, 2006 uart timing characterization all parameters listed in this table were laboratory bench charac terized at room temperature on a small sample of parts. no guar antee is implied. the main intent here is to clarify functional operation of the 82c52. 82c52 uart timing characterized with ix = external clock symbol parameter min max units test conditions (15) ts1 co(ix) delay from ix - 30 ns brsr bit d7 = 0 (ix output) (16) ts2 co (brg) delay from ix - 80 ns brsr bit d7 = 1 (brg output) (17) tcy co (brg) clock cycle time 62.5 - ns brsr bit d7 = 1 (brg output), note 1 (18) tdtx sdo delay from co(brg) low - 30 ns note 2 (19) twltl wr low to tbre low - 50 ns note 3 (20) tclth co (brg) low to tbre high - 50 ns notes 3, 4 (21) tihf intr high on flag - 50 ns note 5a, 5b (22) tihm intr high on ms - 50 ns note 5 (23) trlil rd low to intr low - 60 ns (24) tcthx cts high to disable transmit 4tcy + 10 - ns tbr full, note 6 (25) tdrh co (brg) low to dr high - 40 ns note 7 (26) trldl rd low to dr low - 50 ns note 7 (27) twho wr high to rts /dtr active - 50 ns notes: 1. prescaler rate of divide by 1, divisor select rate of ?externa l? (divide by 1). the baud rate clock (co-brg) operates at 16 t imes the user programmed bit rate. for example, at 1200 baud: tcy = 1/(16 x 1200) = 52.1 s. 2. a. with tr (transmitter register) initially empty, td tx occurs from the 5th falling edge of co(brg) after wr goes high. b. with tr initially full, tdtx occurs from the trailing edge of the 16th co(b rg) in the last stop bit provided wr went high by the trailing edge of the 12th co(brg) in the last stop bit. c. with cts high (disable transmit) and tbr full, tdtx occurs from the 5th falling edge of co(brg) after cts goes low. 3. tbre bit d6 in usr is updated each time tbre changes state. 4. a. with tr initially empty, tclth(tbre) occurs from the 4th falling edge of co(brg) after wr goes high. b. with tr initially full, tclth(tbre) occurs from the tr ailing edge of the 15th co(brg) in the last stop bit provided wr went high by the trailing edge of the 12th co(brg) in the last stop bit. c. with cts high (disable transmit) and tbr full, tclth(tbre) occu rs from the 4th falling edge of co(brg) after cts goes low. 5. a. int on tc : inten enabled; usr bit d5(tc) is updated at this time regardless of interrupt configuration. - int on tc occurs from the trailing edge of the 11th co(brg) in the last stop bit if tbr empty at that time. b. intr on receive flags oe, fe, pe, and rbrk: inten enabled; respective usr bits updated at this time regardless of interrupt configura- tion. - int on oe, fe, pe, rbrk occurs from the trailing edge of the 11th co(brg) in the last stop bit. to avoid oe, rd (rbr) must go low by the trailing edge of the 8th co(brg) in the last stop bit. c. intr on ms: inten and mien enabled; usr bit d4(ms) is updat ed at this time regardless of inten/mien. - intr on ms occurs whenever cts or dsr input changes state. 6. tcthx is time before end of last stop bit by which cts must be inactive (high) to prevent trans mission of the character waiting in tbr. 7. dr bit d7 in usr is updated each time dr changes state. t drh always from trailing edge of 11th co(brg) in last stop bit. 82c52 82c52
15 fn2950.3 april 26, 2006 uart timing characterization figure 15. clock (ix) and co timing figure 16. transmitter data figure 17. receiver data ix co(ix) co(brg) tclch (10) tchcl (11) ts1 (15) ts2 (16) tcy (17) co(brg) tx data tdtx (18) 16 co(brg) periods tdtx (18) data bit co(brg) rx data internal data bit 16 co(brg) periods 8 co(brg) periods start bit rx baud counter starts here sample 82c52 82c52
16 fn2950.3 april 26, 2006 figure 18. transmit timing uart timing characterization (continued) co(brg) tbre sdo intr (19) twltl (20) tclth (18) tdtx idle / start bit last stop bit / idle (21) tihf (23) trlil rd wr co(brg) 9/i 10/i 11/i 12/i 13/i 14/i 15/i 16/i i/1 i/2 i/3 8/i 12 13 14 15 16 11 sdo tbre cts 12 start bit (18) tdtx (20) tclth idle disabled last stop bit (24) tcthx note 1 note 5 note 6 note 4 note 2 note 3 82c52 82c52
17 fn2950.3 april 26, 2006 notes: 1. tbre bit d6 in usr is updated each time tbre changes state. 2. a. with tr initially empty, tclth(tbre) occurs from the 4th falling edge of co(brg) after wr goes high. b. with tr initially full, tclth(tbre) occurs from the tra iling edge of the 15th co(brg) in the last stop bit provided wr went high by the trailing edge of the 12th co(brg) in the last stop bit. 3. a. with tr (transmitter register) initially empty, td tx occurs from the 5th falling edge of co(brg) after wr goes high. b. with tr initially full, tdtx occurs from the traili ng edge of the 16th co(brg) in the last stop bit provided wr went high by the trailing edge of the 12th co(brg) in the last stop bit. 4. tcthx is time before end of last stop bit by which cts must be inactive (high) to prevent trans mission of the character waiting in tbr. 5. with cts high (disable transmit) and tbr full, tclth(tbre) oc curs from the 4th falling edge of co(brg) after cts goes low. 6. with cts high (disable transmit) and tbr full, tdtx occurs from the 5th falling edge of co(brg) after cts goes low. figure 19. receive timing uart timing characterization (continued) co(brg) sdi dr intr 11 12 13 14 15 16 1/i 2/i 3/i (23) trlil (26) trldl usr rbr start bit / idle (25) tdrh (21) tihf rd last stop bit note 1 note 2 82c52 82c52
18 fn2950.3 april 26, 2006 figure 20. other timing notes: 1. dr bit d7 in usr is updated each time dr changes state. t drh always from trailing edge of 11th co(brg) in last stop bit. 2. intr on receive flags oe, fe, pe, and rbrk : inten enabled; respective usr bits updated at this time regardless of interrupt configuration. - int on oe, fe, pe, rbrk occurs from the trailing edge of the 11th co(brg) in the last stop bit. to avoid oe, rd (rbr) must go low by the trailing edge of the 8th co(brg) in the last stop bit. 3. intr on ms : inten and mien enabled; usr bit d4(ms) is updated at this time regardless of inten/mien. - intr on ms occurs whenever cts or dsr input changes state. uart timing characterization (continued) intr dsr / cts rd rts / dtr wr (23) trlil (22) tihm msr (27) twho mcr note 3 82c52 82c52
19 fn2950.3 april 26, 2006 burn-in circuits md82c52 cerdip mr82c52 clcc notes: 1. v cc = 5.5v 0.5v gnd = 0v 2. v ih = 4.5v 10% v il = -0.2v to +0.4v 3. component values: r1 = 1.2k ? , 1/4w, 5% r2 = 47k ? , 1/4w, 5% r3 = 10k ? , 1/4w, 5% c1 = 1.0 f nominal c2 = 0.01 f minimum f0 = 100khz 10%, f1 = f0/2, f2 = f1/2 . . . f12 = f11/2 28 27 26 25 24 23 22 21 20 19 18 17 16 15 r1 r2 r2 r2 r2 r2 r2 r2 r2 r2 r2 r2 r2 r1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 r1 r1 r1 r1 r1 r1 r1 r1 r1 gnd vcc/2 v cc vcc/2 a vcc/2 vcc/2 v cc gnd gnd vcc/2 v cc vcc/2 vcc/2 v cc q3 gnd q4 q5 q6 q7 q8 q7 q8 q1 q2 f0 vcc/2 c2 v cc c1 a r3 23 24 25 22 21 20 19 11 3 2 1 4 14 15 16 17 18 12 13 28 27 26 10 5 6 7 8 9 v cc c1 a r3 r1 vcc/2 r1 vcc/2 r1 vcc/2 r1 vcc/2 r1 vcc/2 r1 v cc r2 q5 a r2 q6 r2 q7 r2 q8 r2 q7 r2 q8 r2 q1 r1 v cc gnd r1 r1 vcc/2 r2 f0 r2 q2 r1 v cc gnd r1 r2 v cc r2 gnd r2 q4 q3 c2 82c52
20 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn2950.3 april 26, 2006 die characteristics die dimensions: 178.7 x 187.0 x 19 1mils metallization: type: silicon - aluminum thickness: 11k ? 2k ? glassivation: type: nitrox thickness: 10k ? worst case current density: 2.07 x 10 4 a/cm 2 metallization mask layout 82c52 d0 sd1 intr tbre co d1 cts gnd ix wr rd cso v cc dr rst rts dtr dsr sdo ox d2 d3 d4 d5 d6 d7 a0 a1 82c52

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